1. Field of the Invention
This invention generally relates to methods and systems to adjust the refresh rates for DRAMs. More specifically, the invention relates to such methods and systems that are based on direct measurements of the cell leakage rates of the DRAMs.
2. Prior Art
One major disadvantage of a dynamic random access memory (or DRAM) is that the cells must be refreshed for every certain period of time, or otherwise the data stored in the cells will become invalid. This is because the charges stored in the cells constantly leak away. There are many leakage paths for a storage capacitor. For example, these capacitors could leak through the devices""s diffusion junction areas, through the channel of a transfer gate, or even through the gate itself by tunneling mechanism. The leakage is a function of a number of factors, including chip temperature, process variation, and voltage fluctuations.
As the device dimensions are scaled down, the magnitude of leakage could also be proportionately reduced due to the reduced junction area. For example, if the refresh time for a 16 M DRAM is about 32 ms, the refresh rate can be reduced to half that when similar technology is used to fabricate a 64 M DRAM. However, process variations, for instance, the channel length, the threshold voltage, junction implant, etc. can be slightly different from wafer to wafer, or even across a wafer. For a large chip such as today""s 1Gb or 4 Gb DRAMs, such variations could even occur within a chip.
In addition, when a DRAM is embedded into a processor chip, for example, lower power operation becomes critical. During active mode, when the processor is fully active, the chip temperature can surge to a temperature much higher than that of the stand alone DRAM chip. At such times, in order to preserve the data integrity, higher refresh rates must be implemented. However, when the chip is in a stand-by mode or a sleep mode, the chip temperature could cool significantly. At these times, since the charge leaks less, it is desirable to increase the refresh cycle time so as to reduce the refresh power consumption.
U.S. Pat. No. 5,278,796 teaches a method of using a discrete temperature sensing device to save DRAM power by adjusting the refresh rate based on the temperature of the DRAM array. The temperature sensor is placed in proximity to the DRAM and outputs a voltage that is proportional to the DRAM temperature. A voltage divider is used so that for each increment of 140 mV (or increase in chip temperature by 14 degrees C.), the refresh cycle time is halved.
U.S. Pat. No. 5,446,696 also refers to installation of a temperature sensor in the processor or memory controller to measure the ambient temperature so as to optimize the DRAM refresh time.
U.S. Pat. No. 5,748,328 describe a DRAM array that also has a temperature sensor that generates a signal that indicates chip temperature. A control circuit receives the signal from the temperature sensor and responsively generates a refresh signal to a refresh circuit according to a given ROM look-up table. The table provides multiple entries that indicate the desired refresh rates for particular temperatures.
Therefore, prior art exists that refers to the concept of adjusting DRAM refresh cycle time according to chip temperature. Among this prior art, either discrete or integrated temperature sensor(s) are used to measure the ambient, process or DRAM temperatures. Such temperature information is fed to a refresh circuit to determine the refresh cycle period, so that refresh power is reduced.
However, there are several important disadvantages of this approach. For example, temperature may not be the only factor that causes the charge in the DRAM cells to leak. Other causes, such as process variations, defect density, voltage fluctuation, noise coupling, etc. will all contribute to the cell leakage mechanism. Moreover, monitoring temperature to adjust the refresh rate requires an accurate and reliable temperature sensor. Once fabricated, the sensor must be calibrated, especially the integrated sensor. If the sensors are not accurate, the refresh rate will be out of control. Further, the degradation of sensor quality during the chip life time is also an unknown factor. Important issues need to be investigated, such as whether the sensor survives the bum-in test, and how the sensor material is compatible with the silicon substrate.
Another important disadvantage of the above-discussed prior art approach is the extra cost involved when integrating a temperature sensor on the chip. Normally, extra process steps with different material are required. For example, U.S. Pat. No. 5,154,514 discloses an on-chip temperature sensor using a Schottky barrier diode made with wide-bandgap (e.g. 3,0 V) metal-oxide semiconductor.
An object of this invention is to provide an improved leakage monitor device and method for DRAMs.
Another object of the present invention is to design a DRAM leakage monitor so that it is pre-charged when the chip is entering the self-refresh cycle.
A further object of this invention is to evaluate a leakage monitor cell and to convert the information on the remaining charge level in the cell into digital output signals that will determine the refresh rate for the following refresh cycle.
Another object of the present invention is to provide an individual monitor cell and refresh circuit set for each bank of a DRAM chip. An object of this invention is to provide a low-power leakage monitoring circuit.
These and other objectives are attained with a novel DRAM refresh method and system and with a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the refresh cycle time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized.
The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.
With a preferred embodiment, the leakage monitor device is built physically adjacent to the DRAM array, using the identical process steps, material, and similar device structure. Therefore, this monitor cell should have identical or slightly worse leakage characteristics compared to any of the real cells in the array. The reason that this monitor cell can also be built with a slightly leakier situation than the real cells is that it may represent the worst cell in the array. It can also be built with multiple cells with proper bit-line loading so that the leakage level can be averaged out.
In accordance with one aspect of this invention, the monitor cell is designed so that it is pre-charged when the chip is entering the self-refresh. Then, the monitor cell is evaluated periodically, for example, once every refresh cycle. Here, every cycle means after all the word lines in the array are refreshed once. Since the leakage condition could be changed quite drastically, a proper and conservative evaluation period is recommended. After the evaluations, the monitor cell is automatically recharged again and is held for the following cycle evaluation, and so on.
Another aspect of the invention is to convert the information on the remaining charge level in the cell into digital output signals which will determine the refresh rate for the following refresh cycle. If the leakage level is very high, a gross adjustment to speed up the refresh rate is issued. In contrast, if the leakage rate is extremely low, a gross adjustment to slow down the refresh rate is issued. If the leakage rate is moderate and within a reasonable range, multiple-steps of minor adjustments on the refresh rate are issued.
In accordance with another aspect of the present invention, an individual monitor cell and refresh circuit set are provided for each bank of a DRAM chip. As a result, each bank can adjust its refresh rate independently based on its local leakage information. Further, monitor cells and refresh circuits sets can be provided on each of the arrays of an embedded memory chip. Such monitor cells can also be built on every chip installed on a module acting as a leakage censor of the chips.
In addition, preferably, the leakage monitoring circuits disclosed herein are low-power circuits. The total power used for these circuit is less than 10 uA, and the power saved by using this feature will be in the mA range, also depending on the applications.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.